LTC4012-3_15 Datasheet, PDF (12/28 Pages) Linear Technology – High Efficiency, Multi-Chemistry Battery Charger with PowerPath Control

LTC4012-3
Operation
Overview
The LTC4012-3 is a synchronous step-down (buck) cur-
rent mode PWM battery charger controller. The maximum
charge current is programmed by the combination of a
charge current sense resistor (R_SENSE), matched input
resistors (R_IN, Figure 1), and a programming resistor
(R_PROG) between the PROG and GND pins. Battery voltage
is programmed with an external resistor divider between
FBDIV and GND. In addition, the PROG pin provides a
linearized voltage output of the actual charge current.
The LTC4012-3 does not have built-in charge termination
and is flexible enough for charging any type of battery
chemistry. It is a building block IC intended for use with
an external circuit, such as a microcontroller, capable of
managing the entire algorithm required for the specific
battery being charged. The LTC4012-3 features a shut-
down input and various state indicator outputs, allowing
easy and direct management by a wide range of external
(digital) charge controllers.
Shutdown
The LTC4012-3 remains in shutdown until DCIN is greater
than 5.1V and exceeds CLP by 60mV and SHDN is driven
above 1.4V. In shutdown, current drain from the battery
is reduced to the lowest possible level, thereby increasing
standby time. When in shutdown, the ITH pin is pulled to
GND and CHRG, ICL, FET gate drivers and INTV_DD are all
disabled. Charging can be stopped at any time by forcing
SHDN below 300mV.
AC Present Detection
AC present is detected as soon as DCIN exceeds BAT by at
least 500mV. Charging is not enabled until this condition is
first met. After this event, charging is no longer gated by
AC present detection. If battery voltage rises due to ESR,
or DCIN droops due to current load, the PWM will remain
enabled, even with very low input overhead, unless DCIN
falls below the supply voltage on CLP.
Input PowerPath Control
The input PFET controller performs many important func-
tions. First, it monitors DCIN and enables the charger
when this input voltage is higher than the raw CLP sys-
tem supply. Next, it controls the gate of an external input
power PFET to maintain a low forward voltage drop when
charging, creating improved efficiency. It also prevents
reverse current flow through this same PFET, providing
a suitable input blocking function. Finally, it helps avoid
synchronous boost operation during invalid operating
conditions by detecting elevated CLP voltage and forcing
the charger off.
If DCIN voltage is less than CLP, then DCIN must rise
60mV higher than CLP to enable the charger and activate
the ideal diode control. The gate of the input PFET is
driven to a voltage sufficient to regulate a forward drop
between DCIN and CLP of about 25mV. If the input voltage
differential drops below this point, the FET is turned off
slowly. If the voltage between DCIN and CLP drops to less
than –25mV, the input FET is turned off in less than 6µs
to prevent significant reverse current from flowing back
through the PFET, and the charger is disabled.
Soft-Start
Exiting the shutdown state enables the charger and releases
the ITH pin. When enabled, switching will not begin until
DCIN exceeds BAT by 500mV and ITH exceeds a threshold
that assures initial current will be positive (about 5% to
25% of the maximum programmed current). To limit inrush
current, soft-start delay is created with the compensation
values used on the ITH pin. Longer soft-start times can be
realized by increasing the filter capacitor on ITH, if reduced
loop bandwidth is acceptable. The actual charge current at
the end of soft-start will depend on which loop (current,
voltage or adapter limit) is in control of the PWM. If this
current is below that required by the ITH start-up threshold,
the resulting charge current transient duration depends on
loop compensation but is typically less than 100µs.
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