LTC3722-2_15 Datasheet, PDF (23/28 Pages) Linear Technology – Synchronous Dual Mode Phase Modulated Full Bridge Controllers

LTC3722-1/LTC3722-2
OPERATION
secondary is snubbed. Without snubbing, the secondary
voltage can ring to levels far beyond what is expected due
to the resonant tank circuit formed between the secondary
leakage inductance and the C_OSS (output capacitance) of
the synchronous rectifier MOSFETs.
Switching Frequency Selection
Unless constrained by other system requirements, the
power converter’s switching frequency is usually set as
high as possible while staying within the desired efficiency
target. The benefits of higher switching frequencies are
many including smaller size, weight and reduced bulk
capacitance. In the full bridge phase-shift converter, these
principles are generally the same with the added complica-
tion of maintaining zero voltage transitions, and therefore,
higher efficiency. ZVS is achieved in a finite time during
the switching cycle. During the ZVS time, power is not
delivered to the output; the act of ZVS reduces the maxi-
mum available duty cycle. This reduction is proportional
to maximum output power since the parasitic capacitive
element (MOSFETs) that increase ZVS time get larger as
power levels increase. This implies an inverse relationship
between output power level and switching frequency.
Table 1 displays recommended maximum switching
frequency vs power level for a 30V/75V in to 3.3V/5V out
converter. Higher switching frequencies can be used if the
input voltage range is limited, the output voltage is lower
and/or lower efficiency can be tolerated.
Table 1. Switching Frequency vs Power Level
<50W
600kHz
<100W
450kHz
<200W
300kHz
<500W
200kHz
<1kW
150kHz
<2kW
100kHz
margin and transient response. Additional modifications
will sometimes be required in order to deal with parasitic
elements within the converter that can alter the feedback
response. The compensation network will vary depending
on the load current range and the type of output capacitors
used. In isolated applications, the compensation network
is generally located on the secondary side of the power
supply, around the error amplifier of the opto-coupler
driver, usually an LT1431 or equivalent. In nonisolated
systems, the compensation network is located around
the LTC3722-1/LTC3722-2’s error amplifier.
In current mode control, the dominant system pole is
determined by the load resistance (V_O/I_O) and the output
capacitor 1/(2π • R_O • C_O). The output capacitors ESR
1/(2π • ESR • C_O) introduces a zero. Excellent DC line and
load regulation can be obtained if there is high loop gain
at DC. This requires an integrator type of compensator
around the error amplifier. A procedure is provided for
deriving the required compensation components. More
complex types of compensation networks can be used to
obtain higher bandwidth if necessary.
Step 1. Calculate location of minimum and maximum
output pole:
F_{P1(M I N)}
=
(2π
•
1
R_{O(M A X )}
•
C_O )
F_{P1(M A X )}
=
(2π
1
• R_O(MIN)
• C_O)
Step 2. Calculate ESR zero location:
F_Z1
=
(2π
•
1
R_ESR
•
C_O
)
Step 3. Calculate the feedback divider gain:
R_B
or ^VREF
(R_B + R_T ) V_OUT
Closing the Feedback Loop
Closing the feedback loop with the full bridge converter
involves identifying where the power stage and other
system poles/zeroes are located and then designing a com-
pensation network around the converters error amplifier
to shape the frequency response to insure adequate phase
If polymer electrolytic output capacitors are used, the ESR
zero can be employed in the overall loop compensation
and optimum bandwidth can be achieved. If aluminum
electrolytics are used, the loop will need to be rolled off
prior to the ESR zero frequency, making the loop response
slower. A linearized SPICE macromodel of the control
372212fb
For more information www.linear.com/LTC3722
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