LTC3722-2_15 Datasheet, PDF(14/28 Page) Linear Technology – Synchronous Dual Mode Phase Modulated Full Bridge Controllers

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LTC3722-2_15 Datasheet, PDF (14/28 Pages) Linear Technology – Synchronous Dual Mode Phase Modulated Full Bridge Controllers

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LTC3722-1/LTC3722-2

OPERATION

network to implement. If there is not enough energy to

fully commutate the bridge leg to a ZVS condition, the

LTC3722-1/LTC3722-2 automatically overrides the Di-

rectSense circuitry and forces a transition. The override

or default delay time is programmed with a resistor from

DPRG to VREF .

Adaptive Mode

The LTC3722-1/LTC3722-2 are configured for adaptive

delay sensing with three pins, ADLY, PDLY and SBUS.

ADLY and PDLY sense the active and passive delay legs

respectively via a voltage divider network, as shown in

Figure 2.

VIN

SBUS

PDLY

ADLY

RCS

372212 F02

Figure 2. Adaptive Mode

delays exist between the time at which the LTC3722â1/

LTC3722-2 controller output transitions, to the time at

which the power MOSFET switches on due to MOSFET

turn-on delay and external driver circuit delay. Ideally, we

want the power MOSFET to switch at the instant there

is zero volts across it. By setting a threshold voltage for

ADLY and PDLY corresponding to several volts across the

MOSFET, the LTC3722-1/LTC3722-2 can anticipate a zero

voltage VDS and signal the external driver and switch to

turn-on. The amount of anticipation can be tailored for

any application by modifying the upper divider resistor(s).

The LTC3722-1/LTC3722-2 DirectSense circuitry sources

a trimmed current out of PDLY and ADLY (proportional

to SBUS) after a low to high level transition occurs. This

provides hysteresis and noise immunity for the PDLY and

ADLY circuitry, and sets the high to low threshold on ADLY or

PDLY to nearly the same level as the low to high threshold,

thereby making the upper and lower MOSFET VDS switch

points virtually identical, independent of VIN.

Example: VIN = 48V nominal (36V to 72V)

1. Set up SBUS: 1.5V is desired on SBUS with VIN = 48V.

Set divider current to 100ÂµA.

R1=

1.5V

100ÂµA

15k

The threshold voltage on PDLY and ADLY for both the ris-

ing and falling transitions is set by the voltage on SBUS.

A buffered version of this voltage is used as the threshold

level for the internal DirectSense circuitry. At nominal VIN,

the voltage on SBUS is set to 1.5V by an external voltage

divider between VIN and GND, making this voltage directly

proportional to VIN. The LTC3722-1/LTC3722-2 DirectSense

circuitry uses this characteristic to zero voltage switch

all of the external power MOSFETs, independent of input

voltage.

ADLY and PDLY are connected through voltage dividers to

the active and passive bridge legs respectively. The lower

resistor in the divider is set to 1k. The upper resistor in

the divider is selected for the desired positive transition

trip threshold.

R2 =

48V â 1.5V

100ÂµA

465k

An optional small capacitor (0.001ÂµF) can be added

across R1 to decouple noise from this input.

2. Set up ADLY and PDLY: 7V of anticipation is desired

in this circuit to account for the delays of the external

MOSFET driver and gate drive components.

R3, R4 = 1k, sets a nominal 1.5mA in the divider chain

at the threshold.

R5, R6

(48V â 7V â 1.5V)

1.5mA

26.3k,

use (2) equal 13k segments.

To set up the ADLY and PDLY resistors, first determine at

what drain to source voltage to turn-on the MOSFETs. Finite

372212fb

For more information www.linear.com/LTC3722

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