LTC3722-2_15 Datasheet, PDF (15/28 Pages) Linear Technology – Synchronous Dual Mode Phase Modulated Full Bridge Controllers

LTC3722-1/LTC3722-2
OPERATION
Fixed Delay Mode
Powering the LTC3722-1/LTC3722-2
The LTC3722-1/LTC3722-2 provides the flexibility through
the SBUS pin to disable the DirectSense delay circuitry
and enable fixed ZVS delays. The level of fixed ZVS delay
is proportional to the voltage programmed through the
voltage divider on the PDLY and ADLY pins (see Figure 3
for more detail).
V_REF
SBUS
PDLY
ADLY
R1
R2
R3
372212 F03
The LTC3722-1/LTC3722-2 utilize an integrated V_CC shunt
regulator to serve the dual purposes of limiting the volt-
age applied to V_CC as well as signaling that the chip’s bias
voltage is sufficient to begin switching operation (under-
voltage lockout). With its typical 10.2V turn-on voltage
and 4.2V UVLO hysteresis, the LTC3722-1/LTC3722-2
is tolerant of loosely regulated input sources such as an
auxiliary transformer winding. The V_CC shunt is capable
of sinking up to 25mA of externally applied current. The
UVLO turn-on and turn-off thresholds are derived from
an internally trimmed reference making them extremely
accurate. In addition, the LTC3722-1/LTC3722-2 exhibits
very low (145µA typ) start-up current that allows the use
of 1/8W to 1/4W trickle charge start-up resistors.
Figure 3. Setup for Fixed ZVS Delays
Programming Adaptive Delay Time-Out
The LTC3722-1/LTC3722-2 controllers include a feature to
program the maximum time delay before a bridge switch
turn on command is summoned. This function will come
into play if there is not enough energy to commutate a
bridge leg to the opposite supply rail, therefore bypass-
ing the adaptive delay circuitry. The time delay can be
set with an external resistor connected between DPRG
and V_REF (see Figure 4). The nominal regulated voltage
on DPRG is 2V. The external resistor programs a current
which flows into DPRG. The delay can be adjusted from
approximately 35ns to 300ns, depending on the resistor
value. If DPRG is left open, the delay time is approximately
400ns. The amount of delay can also be modulated based
on an external current source that feeds current into DPRG.
Care must be taken to limit the current fed into DPRG to
350µA or less.
V_REF
R_{DPRG DPRG}
The trickle charge resistor should be selected as follows:
R_{S T A R T(M A X )}
=
V_{I N(M I N)}
−
10.7V
250µA
Adding a small safety margin and choosing standard
values yields:
APPLICATION
DC/DC
Off-Line
PFC Preregulator
V_IN RANGE
36V TO 72V
85V to 270V_RMS
390V_DC
R_START
100k
430k
1.4M
V_CC should be bypassed with a 0.1µF to 1µF multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the V_CC supply before
the bootstrap winding, or an auxiliary regulator circuit
takes over.
C_{H O L D U P}
=
(I_CC + I_DRIVE )
•
t_DELAY
3.8V
(minimum UVLO hysteresis)
+
V 2V
–
+
SBUS –
TURN-ON
OUTPUT
372212 F04
Figure 4. Delay Timeout Circuitry
372212fb
For more information www.linear.com/LTC3722
15