LTC3829_15 Datasheet, PDF (22/40 Pages) Linear Technology – 3-Phase, Single Output Synchronous Step-Down DC/DC Controller with Diffamp

LTC3829
APPLICATIONS INFORMATION
driver resistance (approximately 2Ω at V_GS = V_MILLER), V_IN
is the drain potential and the change in drain potential in
the particular application. V_TH(IL) is the data sheet speci-
fied typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. C_MILLER
is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.
Both MOSFETs have I²R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V_IN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for V_IN > 20V, the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_MILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes conduct during the dead
time between the conduction of the two large power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead
time and requiring a reverse-recovery period which could
cost as much as several percent in efficiency. A 2A to 8A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition loss due to
their larger junction capacitance.
C_IN and C_OUT Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V_OUT/
V_IN. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a close form
equation can be found in Application Note 77. Figure 10
shows the input capacitor ripple current for different phase
configurations with the output voltage fixed and input volt-
age varied. The input ripple current is normalized against
the DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(V_OUT), is approximately equal to the
input voltage V_IN or:
V_{OUT =} k _{where k= 1, 2,...,N– 1}
V_IN N
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages. In
the graph of Figure 10, the local maximum input RMS
capacitor currents are reached when:
V_{OUT =} 2k– 1 _{where k= 1, 2,...,N}
V_IN N
These worst-case conditions are commonly used for design
because even significant deviations do not offer much relief.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
capacitor manufacturer if there is any question.
3829fc
22
For more information www.linear.com/LTC3829