LTC3829_15 Datasheet, PDF (21/40 Pages) Linear Technology – 3-Phase, Single Output Synchronous Step-Down DC/DC Controller with Diffamp

LTC3829
APPLICATIONS INFORMATION
Power MOSFET and Schottky Diode
(Optional) Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N‑channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and on-resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an output voltage that
is less than 1/3 of the input voltage. In applications where
V_IN >> V_OUT , the top MOSFETs’ on-resistance is normally
less important for overall efficiency than its input capaci-
tance at operating frequencies above 300kHz. MOSFET
manufacturers have designed special purpose devices that
provide reasonably low on-resistance with significantly
reduced input capacitance for the main switch application
in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by the
voltage, V_CC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV_DSS specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less. Selection
criteria for the power MOSFETs include the on-resistance,
R_DS(ON), input capacitance, input voltage and maximum
output current. MOSFET input capacitance is a combina-
tion of several components but can be taken from the
typical gate charge  curve included on most data sheets
(Figure 9). The curve is generated by forcing a constant
input current into the gate of a common source, current
source loaded stage and then plotting the gate voltage
versus time.
V_IN
MILLER EFFECT
V_GS
a
b
Q_IN
C_MILLER = (Q_B – Q_A)/V_DS
V
+
V_G–S
+
– ^VDS
3729 F09
Figure 9. Gate Charge Characteristic
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given V_DS drain
voltage, but can be adjusted for different V_DS voltages by
multiplying the ratio of the application V_DS to the curve
specified V_DS values. A way to estimate the C_MILLER term
is to take the change in gate charge from points a and b
on a manufacturer’s data sheet and divide by the stated
V_DS voltage specified. C_MILLER is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. C_RSS and C_OS are specified sometimes but
definitions of these parameters are not included. When the
controller is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
MainSwitchDuty Cycle= ^VOUT
V_IN
Synchronous
SwitchDuty
Cycle=


V_IN
– V_OUT
V_IN


The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P_MAIN =
V_OUT
V_IN


I_MAX
N


2
(1+ δ)R_DS(ON)
+
(
) V_IN ²


I_MAX
2


(R_DR
)(C_MILLER
)
•



V_CC
–
1
V_TH(IL)
+
1
V_TH(IL)



•f
P_SYNC
=
V_IN – V_OUT
V_IN


I_MAX
N


2
(1+
)δ R_DS(ON)
where N is the number of output stages, δ is the tem-
perature dependency of R_DS(ON), R_DR is the effective top
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