LTC3720_15 Datasheet, PDF (22/24 Pages) Linear Technology – Single Phase VRM8.5 Current Mode Step-Down Controller

LTC3720
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the controller.
These items are also illustrated in Figure 11.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
• Place M2 as close to the controller as possible, keeping
the SENSE^–, BG and SENSE⁺ traces short.
• Connect the input capacitor(s) C_IN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current. Minimize the loop area formed by C_IN, M1 and
M2.
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTV_CC decoupling capacitor C_VCC closely
to the INTV_CC and PGND pins.
• Connect the top driver boost capacitor C_B closely to the
BOOST and SW pins.
• Connect the V_IN pin decoupling capacitor C_F closely to
the V_IN and PGND pins.
• VID0-VID4 interface circuitry must return to SGND.
INT V_CC
POWER GOOD
C_SS
C_C2
R_C
C_ION
R_ON
INT V_CC
C_C1
V_IN
1
RUN/SS
28
BOOST
2
V_ON
27
TG
3
PGOOD
26
SW
4
V_RNG
25
SENSE⁺
5
FCB
24
SENSE^–
6
I_TH
23
PGND
7
LTC3720
22
SGND
BG
8
I_ON
9
V_FB
10
SGND
11
V_FB
12
V_OSENSE
21
INTV_CC
20
V_IN
19
EXTV_CC
18
V_CC
17
VID4
13
VID0
16
VID3
14
VID1
15
VID2
BOLD LINES INDICATE HIGH CURRENT PATHS
V_IN
R_F
10Ω
C_B
C_IN
M1
D_B
M2
+
L1
1µH
V_OUT
D1 +
C_OUT
SGND
C_F
3720 F11
Figure 11. LTC3720 Layout Diagram
3720f
22