LTC3709 Datasheet, PDF (21/24 Pages) Linear Technology – Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing

LTC3709
APPLICATIO S I FOR ATIO
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point, which is then tied to a “clean” point in the
power ground such as the “–” node of C_IN.
• Minimize impedance between input ground and output
ground.
• Connect PGND1 to the source of M2 or R_S1 (QFN)
directly. This also applies to channel 2.
• Place M2 as close to the controller as possible, keeping
the PGND1, BG1 and SW1 traces short. The same for
the other channel. SW2 trace should connect to the
drain of M2 directly.
• Connect the input capacitor(s) C_IN close to the power
MOSFETs: (+) node to drain of M1, (–) node to source
of M2. This capacitor carries the MOSFET AC current.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the DRV_CC decoupling capacitor C_VCC closely
to the DRV_CC and PGND pins.
• Connect the top driver boost capacitor C_B closely to the
BOOST and SW pins.
• Connect the V_IN pin decoupling capacitor C_F closely to
the V_CC and PGND pins.
• Are the SENSE^– and SENSE⁺ leads routed together with
minimum PC trace spacing? The filter capacitor be-
tween SENSE^– and SENSE⁺ (C_SENSE) should be as close
as possible to the IC. Ensure accurate current sensing
with Kelvin connections at the sense resistor as shown
in Figure 8.
D
G
D
S
D
S
D
S
SENSE ⁺ SENSE ^–
MOSFET
(8a) Sensing the Bottom MOSFET
Figure 8. Kelvin Sensing
SENSE ⁺ SENSE ^–
(8b) Sensing a Resistor
R_SENSE
3709 F08
3709f
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