LTC3709 Datasheet, PDF (19/24 Pages) Linear Technology – Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing

LTC3709
APPLICATIO S I FOR ATIO
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3709 circuits:
1. DC I²R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same R_DS(ON), then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I²R
loss. For example, if R_DS(ON) = 0.01Ω and R_L = 0.005Ω, the
loss will range from 0.1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci-
tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Transition Loss ≈ (0.5) • V_IN2 • I_OUT • C_RSS • f •
⎛
R_{DS(ON)_DRV ⎝⎜ DRVCC}
1
− V_GS(TH)
+
1^⎞
V_{GS(TH) ⎠⎟}
3. Gate driver supply current. The driver current supplies
the gate charge Q_G required to switch the power MOSFETs.
This current is typically much larger than the control
circuit current. In continuous mode operation:
I_GATECHG = f (Q_g(TOP) + Q_g(BOT))
4. C_IN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I²R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including C_OUT ESR loss, Schottky conduc-
tion loss during dead time and inductor core loss generally
account for less than 2% additional loss.
When making any adjustments to improve efficiency, the
final arbiter is the total input current for the regulator at
your operating point. If you make a change and the input
current decreases, then you improved the efficiency. If
there is no change in input current, then there is no change
in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to ∆I_LOAD (ESR), where ESR is the effective series
resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT generating a feedback error signal used by
the regulator to return V_OUT to its steady-state value.
During this recovery time, V_OUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lems. The I_TH pin external components shown in Figure 9
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: V_IN = 7V to 28V (15V nominal), V_OUT =
2.5V, I_OUT(MAX) = 20A, f = 250kHz. First, calculate the
timing resistor:
R_ON
=
2.5V
(^0.7V)(^250kHz)(^30pF)
=
476k
and choose the inductor for about 40% ripple current at
the maximum V_IN. Maximum output current for each
channel is 10A:
L
=
2.5V
(^250kHz)(^0.4)(^10A)
⎛⎝⎜_1−
2.5V
28V
⎞⎠⎟
=
2.3µH
3709f
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