LTC3709 Datasheet, PDF (20/24 Pages) Linear Technology – Fast 2-Phase, No RSENSE Synchronous DC/DC Controller with Tracking/Sequencing

LTC3709
APPLICATIO S I FOR ATIO
Selecting a standard value of 1.8µH results in a maximum
ripple current of:
∆I_L
=
2.5V
(^250kHz)(^1.8µH)
⎛⎝⎜_1–
22.85VV ⎞⎠⎟
=
5.1A
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (R_DS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
q_JA = 40°C/W) yields a nominal sense voltage of:
V_SNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
Tying V_RNG to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80°C above a
70°C ambient with ρ_150°C = 1.5:
I_LIMIT
≥
⎛
⎝⎜
146mV
(^1.5)(^0.010Ω)
+
1
2
(^5.1A)^{⎞⎠⎟}
•
2
=
24A
and double check the assumed T_J in the MOSFET:
P_BOT
=
28
V–
28
2.5V
V
⎛⎝⎜
24A
2
⎞⎠⎟ ² _{(1.5)(0.010 Ω)}
=
1.97 W
T_J = 70°C + (1.97W)(40°C/W) = 149°C
Because the top MOSFET is on for such a short time, an
Si4884 R_DS(ON)(MAX) = 0.0165Ω, C_RSS = 100pF, θ_JA =
40°C/W will be sufficient. Checking its power dissipation
at current limit with ρ_100°C = 1.4:
P_TOP
=
2.5V
28V
⎛⎝⎜
24A
2
⎞⎠⎟
2
(^1.4)(^0.0165Ω)
+
(^1.7)(^28V)²(^12A)(^100pF)(^250kHz)
= 0.30W + 0.40W = 0.7W
T_J = 70°C + (0.7W)(40°C/W) = 98°C
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C_IN is chosen for an RMS current rating of about 10A
at 85°C. The output capacitors are chosen for a low ESR
of 0.013Ω to minimize output voltage changes due to
20
inductor ripple current and load steps. The ripple voltage
will be only:
∆V_OUT(RIPPLE) = ∆I_L(MAX) (ESR)
= (5.1A) (0.013Ω) = 66mV
However, a 0A to 10A load step will cause an output
change of up to:
∆V_OUT(STEP) = ∆I_LOAD (ESR) = (10A) (0.013Ω) = 130mV
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 9.
PC Board Layout Checklist
When laying out a PC board follow one of the two sug-
gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place C_IN, C_OUT, MOSFETs, D1, D2 and inductors all in
one compact area. It may help to have some compo-
nents on the bottom side of the board.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3709.
Use several larger vias for power components.
• Use a compact plane for switch node (SW) to keep EMI
down.
• Use planes for V_IN and V_OUT to maintain good voltage
filtering and to keep power losses low.
• Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power component. You can connect the copper areas to
any DC net (V_IN, V_OUT, GND or to any other DC rail in
your system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller. These items are also illustrated in
Figure 9.
3709f