LTC3822-1 Datasheet, PDF (19/24 Pages) Linear Technology – No RSENSE, Low Input Voltage, Synchronous Step-Down DC/DC Controller

LTC3822-1
APPLICATIONS INFORMATION
components, including a review of control loop theory,
refer to Application Note 76.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25) • (C_LOAD).
Thus a 10µF capacitor would be require a 250µs rise time,
limiting the charging current to about 200mA.
Design Example
For a design example, V_IN will be a 3.3V power supply.
Output voltage is 1.8V with a load current requirement
of 8A. The IPRG pin will be tied to V_IN and PLLLPF will
be left floating, so the maximum current sense threshold
ΔV_SENSE(MAX) will be approximately 200mV and the switch-
ing frequency will be 550kHz.
Duty Cycle = ^VOUT = 54.5%
V_IN
From Figure 1, SF = 88%.
R_DS(ON)MAX
=
5
6
• 0.9
•
SF
•
∆V_SENSE(MAX)
I_OUT(MAX) • ρ_T
=
0.013Ω
The Si4466DY has an R_DS(ON) of 0.013Ω. To prevent
inductor saturation during a short circuit, the inductor
current rating should be higher than 16A.
For 3.2A I_RIPPLE, the required minimum inductor value
is:
L_MIN
=
1.8V
550kHz •
4A
•
⎛⎝⎜_1–
1.8V⎞
3.3V⎠⎟
=
0.47µH
A Vishay IHLP2525CZ-01 (0.47µH, 17.5A) inductor works
well for this application.
C_IN will require an RMS current rating of at least 5A
at temperature. A low ESR ceramic C_OUT will allow ap-
proximately 15mV output ripple. Figure 10 shows an 8A,
3.3V_IN/1.8V_OUT application.
PC Board Layout Checklist
When laying out the printed circuit board, use the following
checklist to ensure proper operation of the LTC3822-1.
Figure 9 shows a suggested PCB floorplan.
• The power loop (input capacitor, MOSFET, inductor,
output capacitor) and high di/dt loop (V_IN, through
both MOSFETs to power GND and back through C_IN
to V_IN) should be as small as possible and located on
one layer. Excess inductance here can cause increased
stress on the MOSFETs and increased high frequency
ringing on the output.
• Put the feedback resistors close to the V_FB pins. The I_TH
compensation components should also be very close
to the LTC3822-1. All small-signal circuitry should be
isolated from the main switching loop with ground
Kelvin connected to the output capacitor ground.
• The current sense traces (V_IN and SW) should be Kelvin
connected right at the topside MOSFET source and
drain. The positive current sense pin is shared with
the V_IN pin. This must not be locally decoupled with a
capacitor.
• Keep the switch node (SW) and the gate driver nodes
(TG, BG) away from the small-signal components, es-
pecially the feedback resistors, and I_TH compensation
components.
• Place C_B as close as possible to the SW and BOOST
pins. This capacitor carries high di/dt MOSFET gate
drive currents. The charging current to the boost diode
should be provided from a separate V_IN trace than that
to the V_IN pin.
• Beware of ground loops in multiple layer PC boards. Try
to maintain one central signal ground node on the board.
If the ground plane must be used for high DC currents,
keep that path away from small-signal components.
38221f
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