LTC3822-1 Datasheet, PDF (18/24 Pages) Linear Technology – No RSENSE, Low Input Voltage, Synchronous Step-Down DC/DC Controller

LTC3822-1
APPLICATIONS INFORMATION
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3822-1 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase. The
minimum on-time for the LTC3822-1 is typically about
170ns. However, as the peak sense voltage (I_L(PEAK) •
R_DS(ON)) decreases, the minimum on-time gradually
increases up to about 260ns.
4) Transition losses apply to the external MOSFET and
increase with higher operating frequencies and input
voltages. Transition losses can be estimated from:
Transition Loss = 2 • V_IN2 • I_O(MAX) • C_RSS • f
Other losses, including C_IN and C_OUT ESR dissipative losses
and inductor core losses, generally account for less than
2% total additional loss.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power. It is often useful
to analyze individual losses to determine what is limiting
efficiency and which change would produce the most
improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3822-1 circuits: 1) LTC3822-1 DC bias
current, 2) MOSFET gate charge current, 3) I²R losses
and 4) transition losses.
1) The V_IN (pin) current is the DC supply current, given
in the Electrical Characteristics, which excludes MOSFET
driver currents. V_IN current results in a small loss that
increases with V_IN.
2) MOSFET gate charge current results from switching
the gate capacitance of the power MOSFET. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from BOOST to ground. The
resulting dQ/dt is a current out of BOOST, which is typically
much larger than the VIN supply current. In continuous
mode, I_GATECHG = f • Q_P.
3) I²R losses are calculated from the DC resistances of the
MOSFETs, inductor and/or sense resistor. In continuous
mode, the average output current flows through L but
is “chopped” between the top MOSFET and the bottom
MOSFET. Each MOSFET’s R_DS(ON) can be multiplied by its
respective duty cycle and summed together with the DCR
of the inductor to obtain I²R losses.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to (ΔI_LOAD) • (ESR), where ESR is the effective se-
ries resistance of C_OUT. ΔI_LOAD also begins to charge or
discharge C_OUT generating a feedback error signal used
by the regulator to return V_OUT to its steady-state value.
During this recovery time, V_OUT can be monitored for
overshoot or ringing that would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values.
The I_TH series RC-CC filter (see the Functional Diagram)
sets the dominant pole-zero loop compensation.
The I_TH external components showed in the figure on the
first page of this data sheet will provide adequate compen-
sation for most applications. The values can be modified
slightly (from 0.2 to 5 times their suggested values) to
optimize transient response once the final PC layout is done
and the particular output capacitor type and value have
been determined. The output capacitor needs to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1µs to 10µs will produce output voltage and I_TH
pin waveforms that will give a sense of the overall loop
stability. The gain of the loop will be increased by increas-
ing RC and the bandwidth of the loop will be increased
by decreasing CC. The output voltage settling behavior is
related to the stability of the closed-loop system and will
demonstrate the actual overall supply performance. For
a detailed explanation of optimizing the compensation
38221f
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