LTC3822-1 Datasheet, PDF (17/24 Pages) Linear Technology – No RSENSE, Low Input Voltage, Synchronous Step-Down DC/DC Controller

LTC3822-1
APPLICATIONS INFORMATION
The selection of C_OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔV_OUT) is approximated by:
V_OUT
≈
I_RIPPLE
•
⎛
⎝⎜^ESR
+
8
•
f
1^⎞
• C_{OUT ⎠⎟}
where f is the operating frequency, C_OUT is the output
capacitance and I_RIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I_RIPPLE increase with input voltage.
Topside MOSFET Drive Supply (C_B, D_B)
In the Functional Diagram, external bootstrap capaci-
tor C_B is charged from a boost power source (usually
V_IN) through diode D_B when the SW node is low. When
a MOSFET is to be turned on, the C_B voltage is applied
across the gate source of the desired device. When the
topside MOSFET is on, the BOOST pin voltage is above
the input supply. V_BOOST = 2V_IN. C_B must be 100 times
the total input capacitance of the topside MOSFET. The
reverse breakdown of D_B must be greater than V_IN(MAX).
Note that in applications where the supply voltage to C_B
exceeds V_IN, the boost pin will draw approximately 500µA
in shutdown mode.
Setting Output Voltage
The LTC3822-1 output voltage is set by an external feed-
back resistor divider carefully placed across the output,
as shown in Figure 7. The regulated output voltage is
determined by:
V_OUT
=
0.6V
•
⎛
⎝⎜¹⁺
R_B ⎞
R_A ⎠⎟
For most applications, a 59k resistor is suggested for R_A.
In applications where minimizing the quiescent current is
critical, R_A should be made bigger to limit the feedback
divider current. If R_B then results in very high impedance,
it may be beneficial to bypass R_B with a 10pF to 100pF
capacitor C_FF.
V_OUT
LTC3822-1
V_FB
R_B
C_FF
R_A
38221 F07
Figure 7. Setting the Output Voltage
Low Input Supply Voltage
Although the LTC3822-1 can function down to below
2.4V, the maximum allowable output current is reduced
as V_IN decreases below 3V. Figure 8 shows the amount
of change as the supply is reduced down to 2.4V. Also
shown is the effect on V_REF.
105
V_REF
100
95
MAXIMUM
SENSE VOLTAGE
90
85
80
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
38221 F08
Figure 8. Line Regulation of V_REF and Maximum Sense Voltage
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest amount of
time that the LTC3822-1 is capable of turning the top
MOSFET on. It is determined by internal timing delays
and the gate charge required to turn on the top MOSFET.
Low duty cycle and high frequency applications may ap-
proach the minimum on-time limit and care should be
taken to ensure that:
t_ON(MIN)
<
V_OUT
f_OSC • V_IN
38221f
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