LTC3822-1 Datasheet, PDF (15/24 Pages) Linear Technology – No RSENSE, Low Input Voltage, Synchronous Step-Down DC/DC Controller

LTC3822-1
APPLICATIONS INFORMATION
over temperature and process variations, to be between
250kHz and 750kHz. A simplified block diagram is shown in
Figure 6.
If the external clock frequency is greater than the internal
oscillator’s frequency, f_OSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f_OSC, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor C_LP holds the voltage.
1200
1000
800
600
400
200
0
0.2
0.7
1.2
1.7
2.2
PLLLPF PIN VOLTAGE (V)
38221 F05
Figure 5. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
EXTERNAL
OSCILLATOR
SYNC/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
2.4V
R_LP
C_LP
PLLLPF
OSCILLATOR
38221 F06
Figure 6. Phase-Locked Loop Block Diagram
The loop filter components, C_LP and R_LP, smooth out
the current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. These filter
components determine how fast the loop acquires lock.
Typically R_LP = 10k and C_LP is 2200pF to 0.01µF.
Typically, the external clock (on SYNC/MODE pin) input
high level is 1.6V, while the input low level is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2. The States of the PLLLPF Pin
PLLLPF PIN
SYNC/MODE PIN
0V
DC Voltage
Floating
DC Voltage
V_IN
DC Voltage
RC Loop Filter Clock Signal
FREQUENCY
300kHz
550kHz
750kHz
Phase-Locked
to External Clock
Using a Sense Resistor (GN Only)
A sense resistor R_SENSE can be connected between V_IN and
SENSE^– to sense the output load current. In this case, the
drain of the topside N-channel MOSFET is connected to
SENSE^– pin and the source is connected to the SW pin of
the LTC3822-1. Therefore the current comparator moni-
tors the voltage developed across R_SENSE, not the V_DS of
the top MOSFET. The output current that the LTC3822-1
can provide in this case is given by:
I_OUT(MAX)
=
∆V_SENSE(MAX)
R_SENSE
–
I_RIPPLE
2
Setting ripple current as 40% of I_OUT(MAX) and using
Figure 1 to choose SF, the value of R_SENSE is:
R_SENSE
=
5
6
•
SF
•
∆V_SENSE(MAX)
I_OUT(MAX)
Variation in the resistance of a sense resistor is much
smaller than the variation in on-resistance of an external
MOSFET. Therefore the load current is well controlled
with a sense resistor. However the sense resistor causes
I²R losses in addition to those of the MOSFET. Therefore,
using a sense resistor lowers the efficiency of LTC3822-1,
especially at high load current.
38221f
15