LTC3727LX-1_15 Datasheet, PDF (19/28 Pages) Linear Technology – High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator

LTC3727LX-1
APPLICATIO S I FOR ATIO
circuit ripple current is determined by the minimum on-
time t_ON(MIN) of the LTC3727LX-1 (less than 200ns), the
input voltage and inductor value:
∆I_L(SC) = t_ON(MIN) (V_IN/L)
The resulting short-circuit current is:
I_SC
=
45mV
R_SENSE
+
1
2
∆I_L(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.
A comparator monitors the output for overvoltage condi-
tions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvolt-
age condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if V_OUT returns to a safe level,
normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regu-
late properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The LTC3727LX-1 has a phase-locked loop comprised of
an internal voltage controlled oscillator and phase detec-
tor. This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency f_O. A voltage applied to the PLLFLTR pin
of 1.2V corresponds to a frequency of approximately
380kHz. The nominal operating frequency range of the
LTC3727LX-1 is 250kHz to 550kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆f_H, is equal to the capture range, ∆f_C:
∆f_H = ∆f_C = ±0.5 f_O (250kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin.
If the external frequency (f_PLLIN) is greater than the oscil-
lator frequency f_0SC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f_0SC, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor C_LP holds the voltage. The
LTC3727LX-1 PLLIN pin must be driven from a low
impedance source such as a logic gate located close to the
pin. When using multiple LTC3727LX-1s for a phase-
locked system, the PLLFLTR pin of the master oscillator
should be biased at a voltage that will guarantee the slave
oscillator(s) ability to lock onto the master’s frequency. A
DC voltage of 0.7V to 1.7V applied to the master oscillator’s
PLLFLTR pin is recommended in order to meet this
requirement. The resultant operating frequency can range
from 310kHz to 470kHz.
The loop filter components (C_LP, R_LP) smooth out the current
pulses from the phase detector and provide a stable input
to the voltage controlled oscillator. The filter components
C_LP and R_LP determine how fast the loop acquires lock.
Typically R_LP =10kΩ and C_LP is 0.01µF to 0.1µF.
Minimum On-Time Considerations
Minimum on-time t_ON(MIN) is the smallest time duration
that the LTC3727LX-1 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
3727lx1fa
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