LTC3536_15 Datasheet, PDF (19/28 Pages) Linear Technology – 1A Low Noise, Buck-Boost DC/DC Converter

LTC3536
Applications Information
negligible (for 40kHz is around –5.7°). However, for loops
with higher crossover frequencies this additional phase
lag should be taken into account when designing the
compensation network.
Loop Compensation Example
This section provides an example illustrating the design of
a compensation network for a typical LTC3536 application
circuit. In this example a 3.3V regulated output voltage is
generated with the ability to supply 300mA load from an
input power source ranging from 1.8V to 5.5V. To optimize
efficiency 1MHz switching frequency has been chosen. In
this application the maximum inductor current ripple will
occur at the highest input voltage. An inductor value of
4.7µH has been chosen to limit the worst-case inductor
current ripple. A low ESR output capacitor with a value
of 22µF is specified to yield a worst-case output voltage
ripple of approximately 10mV (occurring at the worst-case
step-up ratio and maximum load current). In summary, the
key power stage specifications for this LTC3536 example
application are given below:
f = 1MHz
V_IN = 1.8V to 5.5V
V_OUT = 3.3V at 300mA
C_OUT = 22µF,
R_C = 10mΩ
L = 4.7µH,
R_L = 60mΩ
With the power stage parameters specified, the compen-
sation network can be designed. A reasonable approach
is to design the compensation network at this worst-case
corner and then verify that sufficient phase margin exists
across all other operating conditions. In this example ap-
plication, at V_IN = 1.8V and the full 300mA load current,
the right-half plane zero will be located at 100kHz and this
will be a dominant factor in determining the bandwidth of
the control loop.
The first step in designing the compensation network
is to determine the target crossover frequency for the
compensated loop. This example will be designed for a
60° phase margin to ensure adequate performance over
parametric variations and varying operating conditions. As
a result, the target crossover frequency, f_C, will be the point
at which the phase of the buck-boost converter reaches
–180°. It is generally difficult to determine this frequency
analytically, because it is significantly impacted by the Q
factor of the resonance in the power stage. As a result,
it is best determined from a Bode plot of the buck-boost
converter as shown in Figure 10. This Bode plot is for
the LTC3536 buck-boost converter using the previously
specified power stage parameters and was generated from
the small signal model equations using LTspice^® software.
In this case, the phase reaches –180° at 37.8kHz making
f_C = 37.8kHz the target crossover frequency for the com-
pensated loop. From the Bode plot of Figure 9 the gain of
the power stage at the target crossover frequency is –2dB.
At this point in the design process, there are three con-
straints that have been established for the compensation
network. It must have +2dB gain at f_C = 37.8kHz, a peak
phase boost of 60° and the phase boost must be centered
at f_C = 37.8kHz.
An analytical approach can be used to design a compensa-
tion network with the desired phase boost, center frequency
and gain. In general, this procedure can be cumbersome
due to the large number of degrees of freedom in a Type III
compensation network. However the design process can
be simplified by assuming that both compensation zeros
V_O/V_C
30
0
24
–20
18
–40
12
–60
GAIN
6
–80
PHASE
0
–100
–6
–120
–12
–140
–18
–160
–24
–180
–30
–200
–36
–220
–42
1
–240
10
100
1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
3536 F10
Figure 10. Converter Bode Plot, V_IN = 1.8V, I_LOAD = 300mA
3536fa
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