LTC3646-1_15 Datasheet, PDF (17/28 Pages) Linear Technology – 40V, 1A Synchronous Step-Down Converter

LTC3646/LTC3646-1
APPLICATIONS INFORMATION
operation is selected creating the lowest fixed output ripple
at the expense of light load efficiency.
The LTC3646 will detect the presence of the external
clock signal on the MODE/SYNC pin and synchronize the
internal oscillator to the phase and frequency of the in-
coming clock. The presence of an external clock will place
the LTC3646 into forced continuous mode operation. For
proper on-time, connect a resistor corresponding to the
SYNC frequency between the RT pin and SGND (see the
Operating Frequency section). The user should be aware
that a clock with fast edges may drive this pin below the
–0.3V rating of this pin and an R-C filter may be needed
to prevent this condition.
Soft-Start
Soft-start on the LTC3646 is implemented by internally
ramping the reference signal fed to the error amplifier
over approximately a 250µs period. Figure 5 shows the
behavior of the regulator during start-up.
During the soft-start period, the inductor current is not
allowed to reverse and discontinuous operation may occur
under light load conditions.
RUN
5V/DIV
I_L
250mA/DIV
V_OUT
5V/DIV
Output Power Good
The PGOOD output of the LTC3646 is driven by a 63Ω
(typical) open-drain pull-down device. This pin will become
high impedance once the output voltage is within 5% (see
V_PGOOD thresholds) of the target regulation point allow-
ing the voltage at PGOOD to rise via an external pull-up
resistor (100k typical). If the output voltage exits a 7.5%
(see V_PGOOD thresholds) regulation window around the
target regulation point the open-drain output will pull down
with 63Ω output resistance to ground, thus dropping
the PGOOD pin voltage. A filter time of 30μs (typical at
f_O = 2.25MHz) acts to prevent unwanted PGOOD output
changes during V_OUT transient events. This filter time
varies as a function of programmed switching period. The
output voltage must exit the 7.5% regulation window for
approximately 70 switching cycles before the PGOOD pin
pulls to ground (see Figure 6).
NOMINAL OUTPUT
PGOOD
VOLTAGE
V_OUT
–7.5% –5% 0% 5% 7.5%
3646 F06
Figure 6. PGOOD Pin Behavior
I_LOAD = 50mA ^100µs/DIV
3646 F05
Figure 5. Start-Up Waveform
For more information www.linear.com/LTC3646
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