LTC3646-1_15 Datasheet, PDF (14/28 Pages) Linear Technology – 40V, 1A Synchronous Step-Down Converter

LTC3646/LTC3646-1
APPLICATIONS INFORMATION
The design example on the back page uses a DFLS1200
based on its low reverse leakage over the voltage and
temperature ratings of the LTC3646.
Output Voltage Programming
The LTC3646 will adjust the output voltage such that V_FB
equals the reference voltage of 0.6V according to:
V_OUT
=
0.6V ^{}1+
R1
R2 
The desired output voltage is set by the appropriate selec-
tion of resistors R1 and R2 as shown in Figure 2. Choosing
large values for R1 and R2 will result in improved efficiency
but may lead to undesired noise coupling or phase margin
reduction due to stray capacitance at the V_FB node. Care
should be taken to route the FB line away from any noise
source, such as the SW line.
When programming output voltages above 12V, a Schottky
diode connected between BOOST and INTV_CC is needed
(see the Boost Capacitor and Diode section.)
To improve the frequency response of the main control
loop a feedforward capacitor, C_F, may be used as shown
in Figure 2.
V_FB
LTC3646
SGND
V_OUT
R1
C_F
R2
3646 F02
Figure 2. Optional Feedforward Capacitor
Minimum Off-Time/On-Time Considerations
The minimum off-time is the smallest amount of time that
the LTC3646 can turn on the bottom power MOSFET, trip
the current comparator and turn off the power MOSFET.
This time is typically 80ns. For the controlled on-time
current mode control architecture, the minimum off-time
limit imposes a maximum duty cycle of:
DC_(MAX) = 1 – (f_O • t_OFF(MIN))
where f_O is the switching frequency and t_OFF(MIN) is the
minimum off-time. If the maximum duty cycle is surpassed,
due to a dropping input voltage for example, the output
will drop out of regulation. The minimum input voltage to
avoid this dropout condition is:
( ) ^{VIN(MIN) = 1−}
V_OUT
f_O • t_OFF(MIN)
If there is concern about operating near the minimum
off-time limits, consider reducing the frequency to add
margin to the design.
Conversely, the minimum on-time is the smallest dura-
tion of time in which the top power MOSFET can be in
its “on” state. This time is typically 30ns. In continuous
mode operation, the minimum on-time limit imposes a
minimum duty cycle of:
DC_(MIN) = (f_O • t_ON(MIN))
where t_ON(MIN) is the minimum on-time. As the equation
shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint. In the rare cases where the
minimum duty cycle is surpassed, the output voltage will
still remain in regulation, but the switching frequency will
decrease from its programmed value. This is an acceptable
result in many applications, so this constraint may not be
of critical importance in some cases, and high switching
frequencies may be used in the design without any fear
of severe consequences. As the sections on Inductor and
Capacitor Selection show, high switching frequencies allow
the use of smaller board components, thus reducing the
footprint of the application circuit.
14
For more information www.linear.com/LTC3646
36461fb