LTC3568_15 Datasheet, PDF (16/18 Pages) Linear Technology – 1.8A, 4MHz, Synchronous Step-Down DC/DC Converter

LTC3568
Typical Applications
Low Output Voltage, 2mm Height Buck Regulator
V_IN
2.5V
TO 5.5V
C1
22µF
BM
FC
PGND
R_S1
1M
PV_IN
PGOOD
SV_IN
SW
LTC3568
SYNC/MODE
R5
100k
PGOOD
L1
1.7µH
C4 47pF
PS
SGND
R_S2
V_FB
1M
R3
13k
I_TH
SHDN/R_T
SGND PGND
1.8V
R2
1.5V 1.2V 402k
C3
1000pF
R4
R1A R1B R1C
324k
316k 453k 787k
GND
V_OUT
1.2V/1.5V/1.8V
C2 ^{AT 1.8A}
47µF
x2
3568 TA04
C1: TAIYO YUDEN JMK325BJ226MM
C2: TAIYO YUDEN JMK325BJ476MM
L1: SUMIDA CDRH2D18/HP1R7
SGND
Efficiency vs Load Current
95
V_OUT = 1.8V
90
85
V_OUT = 1.2V
80
V_OUT = 1.5V
75
V_IN = 3.3V
Burst Mode OPERATION
70
f_O = 1MHz
1
10
100
1000 10000
LOAD CURRENT (mA)
3568 TA05
Package Description
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 p0.05
R = 0.125
TYP
6
0.40 p 0.10
10
3.55 p0.05
1.65 p0.05
2.15 p0.05 ^{(2 SIDES)}
PIN 1
PACKAGE TOP MARK
OUTLINE (SEE NOTE 6)
0.25 p 0.05
0.50
BSC
2.38 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.200 REF
3.00 p0.10 1.65 p 0.10
(4 SIDES) (2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
0.75 p0.05
(DD) DFN REV C 0310
5
1
0.25 p 0.05
0.50 BSC
0.00 – 0.05
2.38 p0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3568fa
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