LTC3568_15 Datasheet, PDF (11/18 Pages) Linear Technology – 1.8A, 4MHz, Synchronous Step-Down DC/DC Converter

LTC3568
Applications Information
SHDN/R_T
R_T
SHDN/R_T SV_IN
R_T
1M
RUN
RUN
(3a)
RUN OR V_IN I_TH
R1 _D1
R_C
(3b)
C1
(3c)
C_C
3568 F03
Figure 3. SHDN/R_T Pin Interfacing and External Soft-Start
internal digital soft-start which steps up a clamp on I_TH
over 1024 clock cycles, as can be seen in Figure 4.
The soft-start time can be increased by ramping the volt-
age on I_TH during start-up as shown in Figure 3(c). As
the voltage on I_TH ramps through its operating range the
internal peak current limit is also ramped at a proportional
linear rate.
V_IN
5V/DIV
V_OUT
1V/DIV
I_L
1A/DIV
V_IN = 3.3V
V_OUT = 2.5V
I_LOAD = 1.8A
400µs/DIV
3568 F04
Figure 4. Digital Soft-Start
Mode Selection and Frequency Synchronization
The SYNC/MODE pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to V_IN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected
to ground, pulse skipping operation is selected which
provides the lowest output voltage and current ripple
at the cost of low current efficiency. Applying a voltage
between SV_IN – 1V and 1V, results in forced continuous
mode, which creates a fixed output ripple and is capable
of sinking some current (about 1/2ΔI_L). Since the switch-
ing noise is constant in this mode, it is also the easiest to
filter out. In many cases, the output voltage can be simply
connected to the SYNC/MODE pin, giving the forced con-
tinuous mode, except at startup.
The LTC3568 can also be synchronized to an external clock
signal by the SYNC/MODE pin. The internal oscillator fre-
quency should be set to 20% lower than the external clock
frequency to ensure adequate slope compensation, since
slope compensation is derived from the internal oscillator.
During synchronization, the mode is set to pulse skipping
and the top switch turn on is synchronized to the rising
edge of the external clock.
Checking Transient Response
The OPTI-LOOP^® compensation allows the transient
response to be optimized for a wide range of loads and
output capacitors. The availability of the I_TH pin not only
allows optimization of the control loop behavior but also
provides a DC-coupled and AC filtered closed loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
The I_TH external components shown in the Figure 1 circuit
will provide an adequate starting point for most applica-
tions. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1µs
to 10µs will produce output voltage and I_TH pin waveforms
3568fa
11