LTC3568_15 Datasheet, PDF (14/18 Pages) Linear Technology – 1.8A, 4MHz, Synchronous Step-Down DC/DC Converter

LTC3568
Applications Information
Design Example
As a design example, consider using the LTC3568 in a typical
application with V_IN = 5V. The load requires a maximum
of 1.8A in active mode and 10mA in standby mode. The
output voltage is V_OUT = 2.5V. Since the load still needs
power in standby, Burst Mode operation is selected for
good low load efficiency.
First, calculate the timing resistor:
( ) ^R_T ^{= 9.78 • 1011 1MHz −1.08 = 323.8k}
Use a standard value of 324k. Next, calculate the inductor
value for about 40% ripple current at maximum V_IN:
L
=
2.5V
1MHz • 720mA
•


1−
2.5V 
5V 
=
1.7µH
Choosing the closest inductor from a vendor of 2µH,
results in a maximum ripple current of:
ΔI_L
=
2.5V
1MHz • 2µ
•


1−
2.5V
5V


=
625mA
For cost reasons, a ceramic capacitor will be used. C_OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
C_OUT
≈
2.5
1MHz
1.8A
• (5%
•
2.5V)
=
36µF
The closest standard value is 22µF plus 10µF. Since the
supply’s output impedance is very low, C_IN is typically a
22µF. In noisy environments, decoupling SV_IN from PV_IN
with an R6/C8 filter of 1Ω/0.1µF may help, but is typically
not needed.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2µA with the 0.8V feedback voltage makes R1~400k. A
close standard 1% resistor is 412k and R2 is then 887k.
The compensation should be optimized for these compo-
nents by examining the load step response but a good place
to start for the LTC3568 is with a 13kΩ and 1000pF filter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
The PGOOD pin is a common drain output and requires
a pull-up resistor. A 100k resistor is used for adequate
speed.
Figure 1 shows the complete schematic for this design
example.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3568. These items are also illustrated graphically
in the layout diagram of Figure 6. Check the following in
your layout:
C_IN
V_IN
R5
PGOOD
C4
R2 R1 R3
PV_IN
PGND
L1
SV_IN
SW
LTC3568 SGND
PGOOD
V_IN
V_FB
I_TH
SYNC/MODE
SHDN/R_T ^{PS BM}
R_T
C3
C_OUT
V_OUT
BOLD LINES INDICATE HIGH CURRENT PATHS
3568 F06
Figure 6. LTC3568 Layout Diagram (See Board Layout Checklist)
3568fa
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