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| LTC3831_15 Datasheet, PDF (13/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination | |||
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LTC3831
APPLICATIONS INFORMATION
VDDQ
5V
2.5V
MBR0530T1
1μF
PVCC2 PVCC1
VCC
TG
0.1μF
SS
IMAX
+
4.7μF
0.01μF
130k
LTC3831 IFB
FREQSET
BG
SHDN
SHDN
PGND
C1
33pF
COMP
GND
RC
15k
R+
CC
1500pF
Râ
FB
10k
0.1μF
Q1
0.1μF
1k
Q2
CIN: SANYO POSCAP 6TPB330M
COUT: SANYO POSCAP 4TPB470M
Q1, Q2: SILICONIX Si4410DY
MBRS340T3
+ CIN
330μF
Ã2
LO
1.2μH
MBRS340T3
+
VTT
1.5V
±6A
COUT
470μF
Ã3
2k
1%
10k
1%
3831 F08
Figure 8. Typical Application with VTT = 0.6 ⢠VDDQ
Power MOSFETs
Two N-channel power MOSFETs are required for most
LTC3831 circuits. These should be selected based primarily
on threshold voltage and on-resistance considerations.
Thermal dissipation is often a secondary concern in high
efï¬ciency designs. The required MOSFET threshold should
be determined based on the available power supply volt-
ages and/or the complexity of the gate drive charge pump
scheme. In 3.3V input designs where an auxiliary 12V
supply is available to power PVCC1 and PVCC2, standard
MOSFETs with RDS(ON) speciï¬ed at VGS = 5V or 6V can
be used with good results. The current drawn from this
supply varies with the MOSFETs used and the LTC3831âs
operating frequency, but is generally less than 50mA.
LTC3831 applications that use 5V or lower VIN voltage and
doubling/tripling charge pumps to generate PVCC1 and
PVCC2, do not provide enough gate drive voltage to fully
enhance standard power MOSFETs. Under this condition,
the effective MOSFET RDS(ON) may be quite high, raising
the dissipation in the FETs and reducing efï¬ciency. Logic-
level FETs are the recommended choice for 5V or lower
voltage systems. Logic-level FETs can be fully enhanced
with a doubler/tripling charge pump and will operate at
maximum efï¬ciency.
After the MOSFET threshold voltage is selected, choose
the RDS(ON) based on the input voltage, the output voltage,
allowable power dissipation and maximum output current.
In a typical LTC3831 circuit operating in continuous mode,
the average inductor current is equal to the output load
current. This current ï¬ows through either Q1 or Q2 with the
power dissipation split up according to the duty cycle:
DC(Q1)
=
VOUT
VIN
DC(Q2) = 1â
VOUT
VIN
=
VIN
â VOUT
VIN
The RDS(ON) required for a given conduction loss can now
be calculated by rearranging the relation P = I2R.
RDS(ON)Q1 =
PMAX(Q1)
DC(Q1) ⢠(ILOAD )2
=
VIN ⢠PMAX(Q1)
VOUT ⢠(ILOAD )2
RDS(ON)Q 2
=
PMAX(Q2 )
DC(Q2) ⢠(ILOAD)2
=
VIN ⢠PMAX(Q2)
(VIN â VOUT ) ⢠(ILOAD)2
PMAX should be calculated based primarily on required
efï¬ciency or allowable thermal dissipation. A typical high
efï¬ciency circuit designed for 2.5V input and 1.25V at 5A
3831fb
13
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