LTC3831_15 Datasheet, PDF (1/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination

LTC3831
FEATURES
High Power Synchronous
Switching Regulator Controller
for DDR Memory Termination
DESCRIPTION
n _{High Power Switching Regulator Controller}
for DDR Memory Termination
n _{VOUT Tracks 1/2 of VIN or External VREF}
n _{No Current Sense Resistor Required}
n _{Low Input Supply Voltage Range: 3V to 8V}
n _{Maximum Duty Cycle > 91% Over Temperature}
n _{Drives All N-Channel External MOSFETs}
n _{High Efficiency: Over 95% Possible}
n _{Programmable Fixed Frequency Operation:}
100kHz to 500kHz
n _{External Clock Synchronization Operation}
n _{Programmable Soft-Start}
n _{Low Shutdown Current: <10μA}
n _{Overtemperature Protection}
n _{Available in 16-Pin Narrow SSOP Package}
APPLICATIONS
n _{DDR SDRAM Termination}
n _{SSTL_2 Interface}
n _{SSTL_3 Interface}
The LTC^®3831 is a high power, high efficiency switching
regulator controller designed for DDR memory termina-
tion. The LTC3831 generates an output voltage equal
to 1/2 of an external supply or reference voltage. The
LTC3831 uses a synchronous switching architecture
with N-channel MOSFETs. Additionally, the chip senses
output current through the drain-source resistance of the
upper N-channel FET, providing an adjustable current limit
without a current sense resistor.
The LTC3831 operates with input supply voltage as low as
3V and with a maximum duty cycle of > 91%. It includes
a fixed frequency PWM oscillator for low output ripple
operation. The 200kHz free-running clock frequency can
be externally adjusted or synchronized with an external
signal from 100kHz to above 500kHz. In shutdown mode,
the LTC3831 supply current drops to <10μA.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
V_DDQ
5V
2.5V
MBR0530T1
1μF
PV_CC2 PV_CC1
0.1μF
10k
Q1
MBRS340T3
+ C_IN
330μF
×2
V_CC
TG
0.1μF
SS
I_MAX
+
4.7μF
0.01μF
130k
LTC3831 I_FB
FREQSET
BG
SHDN
SHDN
PGND
COMP
GND
C1
33pF
R_C
15k
R⁺
C_C
1500pF
R^–
FB
0.1μF
1k
L_O
1.2μH
Q2
MBRS340T3
+
C_IN: SANYO POSCAP 6TPB330M
C_OUT: SANYO POSCAP 4TPB470M
Q1, Q2: SILICONIX Si4410DY
C_OUT
470μF
×3
V_TT
1.25V
±6A
3831 F01
Figure 1. Typical DDR Memory Termination Application
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20 ^TA ^{= 25°C}
V_IN = 2.5V
10 _{VOUT = 1.25V}
0
0
1
2
3
4
5
6
LOAD CURRENT (A)
2831 G01
3831fb
1