W2350EP Datasheet, PDF (5/12 Pages) Keysight Technologies – High Speed Digital Design

SerDes Modeling and IBIS AMI Model Generation with SystemVue
Two addons for our SystemVue
ESL datalow modeling tool offer
serializer-deserializer (SerDes) models
with (W1714 AMI Modeling Kit)
or without (W1713 SerDes Model
Library) automatic IBIS AMI model
generation.
They let you optimize the signal
processing blocks for your SerDes
integrated circuit (IC) at the elec-
tronic system level (ESL). Once you’ve
designed and optimized the algo-
rithms, the W1714 AMI Modeling Kit
automatically generates an IBIS AMI
model that you can freely distribute
to your customers as an ‘executable
datasheet’ to help them design your
chip into their system.
Use of SystemVue saves time,
reduces engineering effort and
accelerates the maturity of SerDes
designs for next generation multigiga-
bit transceiver (MGTs) in chip-to-chip
serial links. They enable system
architects, algorithm developers and
hardware designers to investigate,
implement and verify their SerDes
signal processing blocks in the
presence of interconnect impairment
models similar to those encountered
in the systems the SerDes will be
designed into. The libraries give
the user piece of mind that their
product meets or exceeds real-world
performance requirements from the
standards association of serial link
like PCI Express, HDMI etc.
These add-ons provides measure-
ment-hardened “golden reference”
models that accelerate the SerDes
design and veriication process. The
tool puts reliable Keysight measure-
ment know-how at the front of the
design process, where it improves
the actual design, instead of only
characterizing nonconformity after
the fact.
In addition to SerDes models, these
product contain a unique optical
iber communication library that
you can use to create a model of a
rack-to-rack optoelectronic link. Using
a pre-standard extension to the AMI
standard, you can export this model
to the mid-channel redriver compo-
nent in ADS Channel Simulator.
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ResponseType=Step Response
TimeStep=1e-12[sample_interval]
Gain=1[Gain]
Input
Output
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BlindFFE
3
Coefficients=0;1;0.[Taps]
SamplesPerBit=16[SamplesPer Bit
Figure 4. The SerDes model blocks can be specified in several way. The taps of the standard FIR block on the left were tuned so that the
step response (blue) matches measured data (red). In contrast, the block on the right was created with custom code.
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