W2350EP Datasheet, PDF (2/12 Pages) Keysight Technologies – High Speed Digital Design

Jump the Gigabit-per-Second Barrier
Today’s high-speed digital designers require EDA tools that accurately
model RF and microwave effects, and that analyze not only signal
integrity, but also the power integrity, and EMI/EMC of serial and
parallel chip-to-chip data links. A prime example is signal integrity on
serial links.
Increasing consumer and business demand for digital entertainment
and information transmission is driving the need for high-speed
systems such as routers, servers, mass storage system, and PCs.
Chip-to-chip connections inside these systems have undergone
an architectural shift from parallel busses to serializer/deserializer
(SerDes) links. Such serial links eliminate parallel bus clock skew and
reduce the number of traces — advantages that come at the cost
of large increases in bit rate on the remaining traces. At data rates
greater than a gigabit per second and with channel light times longer
than a bit period, signal integrity is a major concern. Under these
conditions, high-speed analog effects, previously only seen in high-
frequency RF and microwave engineering, can impair the signal quality
and degrade the bit error rate of the link.
Keysight Technologies, Inc. EEsof EDA has for years been proud to
offer Advanced Design System (ADS) as the premier simulator of
RF and microwave effects. RF and microwave engineers trust ADS
to analyze their circuits and to help them mitigate the impairments
encountered at these frequencies. Now, through continuous research
and innovation, Keysight EEsof EDA offers solutions that put the
applicable simulators, libraries, and capabilities into the hands of high-
speed digital engineers.
These bundles, listed in the table
17.5
below, provide the most complete
chip-to-chip data link analysis for
15.0
On-board
standards such as Ininiband, PCI
12.5
On-chip
Express, RapidIO, DDR, HDMI, and
Ethernet. They allow you to:
10.0
7.5 _{Parallel bus}
5.0
Serial bus
2.5
0
1998 2000 2002 2004 2006 2008 2010 2012 2014 2016
Year
– Analyze complete chip-to-chip
data links by co-simulating
individual components, each
at its most appropriate level
of abstraction: link-, circuit- or
physical-level.
– Import S-parameter accurately
into transient simulation.
– Generate ultra-low bit error rate
(BER) contours in seconds not
days.
Figure 1. Projected increase of clock frequencies Source: ITRS 2004
Update to the SIA Roadmap
These capabilities result in dramati-
cally reduced product design cycles.
The following sections highlight key
features of the elements that make up
these bundles.
2