813N252I-09_15 Datasheet, PDF (7/23 Pages) Integrated Device Technology – VCXO Jitter Attenuator & FemtoClock Multiplier

813N252I-09 Datasheet
Table 4C. Differential DC Characteristics, V_CC = V_CCO = V_CCX = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
I_IH
Input High Current
CLK0, nCLK0,
CLK1, nCLK1
V_CC = V_IN = 3.465V
I_IL
V_PP
V_CMR
Input Low Current
CLK0, CLK1
nCLK0, nCLK1
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1
V_CC = 3.465V, V_IN = 0V
V_CC = 3.465V, V_IN = 0V
-10
-150
0.15
V_EE
NOTE 1: Common mode voltage is defined at the cross point.
Maximum
150
1.3
V_CC – 0.85
Units
µA
µA
µA
V
V
Table 4D. LVPECL DC Characteristics, V_CC = V_CCO = V_CCX = 3.3V ± 5%, V_EE = 0V, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
Units
V_OH
V_OL
V_SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V_CCO – 1.10
V_CCO – 2.0
0.6
V_CCO – 0.75
V
V_CCO – 1.6
V
1.0
V
NOTE 1: Outputs terminated with 50 to V_CCO – 2V. See Parameter Measurement Information section, 3.3V Output Load Test Circuit.
AC Electrical Characteristics
Table 5. AC Characteristics, V_CC = V_CCO = V_CCX = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
f_IN
f_OUT
tjit(Ø)
Input Frequency
Output Frequency
RMS Phase Jitter, (Random),
NOTE 1
125MHz f_OUT, 25MHz crystal,
Integration Range: 12kHz – 20MHz
0.008
25
155.52
312.5
MHz
MHz
0.25
0.35
ps
tjit(pk-pk) Peak-to-Peak Jitter
1e-12 BER
25
ps
tsk(o)
Output Skew; NOTE 2, 3
25
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
140
48
400
ps
52
%
t_LOCK
VCXO & FemtoClock PLL
Lock Time; NOTE 4
6
S
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth.
Refer to VCXO-PLL Loop Bandwidth Selection Table.
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Lock Time measured from power-up to stable output frequency.
©2015 Integrated Device Technology, Inc.
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Revision C, December 10, 2015