813N252I-09_15 Datasheet, PDF (16/23 Pages) Integrated Device Technology – VCXO Jitter Attenuator & FemtoClock Multiplier

813N252I-09 Datasheet
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation of
the VCXO-PLL. In choosing a crystal, special precaution must be
taken with the package and load capacitance (C_L). In addition,
frequency, accuracy and temperature range must also be
considered. Since the pulling range of a crystal also varies with the
package, it is recommended that a metal-canned package like HC49
be used. Generally, a metal-canned package has a larger pulling
range than a surface mounted device (SMD). For crystal selection
information, refer to the VCXO Crystal Selection Application Note.
The crystal’s load capacitance C_L characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (C_TUNE).
If the crystal C_L is greater than the total external capacitance, the
VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal C_L is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than the
crystal specification. In either case, the absolute tuning range is
reduced. The correct value of C_L is dependant on the characteristics
of the VCXO. The recommended C_L in the Crystal Parameter Table
balances the tuning range by centering the tuning curve.
The frequency of oscillation in
the third overtone mode is not
necessarily at exactly three times
the fundamental frequency. The
mechanical properties of the
quartz element dictate the
position of the overtones relative
to the fundamental. The
oscillator circuit may excite both
the fundamental and overtone
modes simultaneously. This will
cause a nonlinearity in the tuning
curve. This potential problem is
LF0
LF1
ISET
R_S R_SET
C_P C_S
C_TUNE
25MHz
C_TUNE
XTAL_IN
XTAL_OUT
why VCXO crystals are required to be tested for absence of any
activity inside a ±200ppm window at three times the fundamental
frequency. Refer to c and F_{L_3OVT_spurs} in the Crystal Characteristics
table.
The crystal and external loop filter components should be kept as
close as possible to the device. Loop filter and crystal traces should
be kept short and separated from each other. Other signal traces
should be kept separate and not run underneath the device, loop filter
or crystal components.
VCXO Characteristics Table
Symbol Parameter
Typical
Units
k_VCXO
VCXO Gain
4.4
C_{V_LOW} Low Varactor Capacitance
8
C_{V_HIGH} High Varactor Capacitance
16
kHz/V
pF
pF
VCXO-PLL Loop Bandwidth Selection Table
Crystal
Frequency
R_S
C_S
C_P R_SET
Bandwidth
(MHz)
M (k) (µF) (µF) (k)
8Hz (Low)
25
3125 680 0.20 0.002 22
20Hz (Mid)
25
3125 470 0.20 0.002 5
75Hz (High)
25
3125 680 0.02 0.003 2.2
NOTE: When configuring the 813N252I-09 with PLL loop bandwidth
less than 75Hz, it is recommended that CLK1, nCLK1 input be used
as the only reference clock. In systems where both reference clocks
are used, it is recommended to have PLL loop bandwidths of 75Hz
or greater.
Crystal Characteristics
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Fundamental
f_N
Frequency
f_T
Frequency Tolerance
f_S
Frequency Stability
Operating Temperature Range
25
MHz
±20
ppm
±20
ppm
-40
85
0_C
C_L
C_O
C_O / C₁
F_{L_3OVT}
F_{L_3OVT_spurs}
ESR
Load Capacitance
Shunt Capacitance
Pullability Ratio
3^rd Overtone F_L
3^rd Overtone F_L Spurs
Equivalent Series Resistance
10
pF
4
pF
220
240
200
ppm
200
ppm
20

Drive Level
1
mW
Aging @ 25 ⁰C
One Year
Ten Year
±3
ppm
±10
ppm
©2015 Integrated Device Technology, Inc.
16
Revision C, December 10, 2015