813N252I-09_15 Datasheet, PDF (15/23 Pages) Integrated Device Technology – VCXO Jitter Attenuator & FemtoClock Multiplier

813N252I-09 Datasheet
Application Schematic Example
Figure 6 shows an example of 813N252I-09 application schematic. In
this example, the device is operated at V_CC = V_CCX = V_CCO = 3.3V. The
decoupling capacitor should be located as close as possible to the
power pin. The input is driven by a 3.3V LVPECL driver. Two
examples of terminations are shown in this schematic. An optional
3-pole filter can also be used for additional spur reduction. It is
recommended that the loop filter components be laid out for the
3-pole option. This will also allow the 2-pole filter to be used.
LVPECL Driv er
Zo = 50
Zo = 50
VCC
R5
R6
125
125
VCC
R1
R2
125
125
CLK1
nCLK1
R3
R4
84
84
LVPECL Driv er
Zo = 50
Zo = 50
CLK0
nCLK0
R7
R8
84
85
C1
TUNE
VCC
C2
TUNE
R12 10
C5
0.01u
VCCX
2-pole loop filter for Mid Bandwidth setting
LF
LF
Rs
470k
Cs
0.2uF
Cp
VCC
0.002uF
C6
10u
CLK_SEL
R15
C8
2.21K
0.1u
XTAL_OUT
X1
XTAL_IN
U1
1
2
3
4
LF1
LF0
ISET
5
6
7
8
VEE
CLK_SEL
VCC
RESERVED
VEE
Logic Control Input Examples
Set Logic
VCC _{Input to}
'1'
RU1
1K
Set Logic
VCC _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VCC
C4
0.1u
VCCO
0.1u
C7
VEE
nQB
QB
24
23
22
21
VCCO
nQA
QA
VEE
20
19
18
17
ODASEL_0
nQB
QB
nQA
QA
ODASEL_0
3.3V
R10
133
Zo = 50 Ohm
R11
133
+
Zo = 50 Ohm
-
R13
R14
82.5
82.5
LVPECL
Termination
VCC = VCCX = VCCO= 3.3V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R16
R17
50
50
3-pole loop filter example - (optional)
R9
LF
LF
Rs
TBDk
470k
Cs
0.2uF
Cp
0.002uF
C3
TBDpF
VCC
C9
0.1u
R19
VCCA 10
VCC
VCC
C10
C11
0.01u
10u
LVPECL
R18
Optional
50
Y-Termination
Figure 6. 813N252I-09 Application Schematic
©2015 Integrated Device Technology, Inc.
15
Revision C, December 10, 2015