IS61WV25616EDBLL-10TLI-TR Datasheet, PDF (9/14 Pages) Integrated Silicon Solution, Inc – 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC

IS61/64WV25616EDBLL
AC WAVEFORMS
1
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) ^(1 )
t WC
2
ADDRESS
t SA
VALID ADDRESS
t SCE
t HA
CE
t AW
3
t PWE1
WE
t PWE2
UB, LB
t PWB
4
t HZWE
t LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t SD
t HD
5
DIN
DATAIN VALID
UB_CEWR1.eps
Notes:
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1.  WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2.  WRITE = (CE) [ (LB) = (UB) ] (WE).
7
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) ^(1,2)
ADDRESS
OE
t WC
VALID ADDRESS
t HA
CE LOW
WE
UB, LB
t SA
DOUT
DATA UNDEFINED
DIN
t AW
t PWE1
t PWB
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
UB_CEWR2.eps
8
9
10
11
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Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. A
09/29/2011