IS61WV25616EDBLL-10TLI-TR Datasheet, PDF (2/14 Pages) Integrated Silicon Solution, Inc – 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC

IS61/64WV25616EDBLL
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read

Write

I/O PIN
WE CE OE LB UB
I/O0-I/O7
I/O8-I/O15
XHXXX
High-Z
High-Z
HLHXX
X
L
X
H
H
High-Z
High-Z
High-Z
High-Z
H
L
L
L
H
Dout
High-Z
H
L
L
H
L
High-Z
Dout
H
L
L
L
L Dout Dout
L
L
X
L
H
Din
High-Z
L
L
X
H
L
High-Z
Din
L
L
X
L
L Din Din
Vdd Current
Isb1, Isb2
Icc
Icc
Icc
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
A0 1
A1 2
A2 3
A3 4
A4 5
CE 6
I/O0 7
I/O1 8
I/O2 9
I/O3 10
VDD 11
GND 12
I/O4 13
I/O5 14
I/O6 15
I/O7 16
WE 17
A5 18
A6 19
A7 20
A8 21
A9 22
*SOJ package under evaluation.
44 A17
43 A16
42 A15
41 OE
40 UB
39 LB
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 GND
33 VDD
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 NC
27 A14
26 A13
25 A12
24 A11
23 A10
PIN DESCRIPTIONS
A0-A17
Address Inputs
I/O0-I/O15
CE
OE
WE
LB
UB
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
NC
No Connection
Vdd
Power
GND
Ground
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011