IS61WV25616EDBLL-10TLI-TR Datasheet, PDF (7/14 Pages) Integrated Silicon Solution, Inc – 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC

IS61/64WV25616EDBLL
AC WAVEFORMS
READ CYCLE NO. 1^(1,2) (Address Controlled) (CE = OE = Vil, UB or LB = Vil)
ADDRESS
DOUT
t RC
PREVIOUS DATA VALID
t OHA
t AA
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2^(1,3)
ADDRESS
OE
CE
LB, UB
tLZCE
DOUT
tLZB
HIGH-Z
tRC
tAA
tOHA
tDOE
tLZOE
tACE
tHZOE
tHZCE
tBA
tRC
tHZB
DATA VALID
VDD
Supply
Current
tPU
50%
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = Vil.
3. Address is valid prior to or coincident with CE LOW transition.
tPD
ICC
50%
ISB
UB_CEDR2.eps
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. A
09/29/2011