IS61QDPB42M36 Datasheet, PDF (9/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs

72 Mb (2M x 36 & 4M x 18)
QUADP (Burst of 4) Synchronous SRAMs
Q
I³
Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.)
Mode
Clock
K
Stop Clock
Stop
No Operation (NOP) L→H
Read B
L →H
Write A
L →H
Controls
Data In
Data Out
RW
D_B
D_B+1
D_B+2
D_B+3
Q_A
Q_A+1
Q_A+2
Q_A+3
X
X
Previous Previous Previous Previous Previous Previous Previous Previous
State State State State
State
State
State
State
HH
X
X
X
X
High-Z High-Z High-Z High-Z
L
X
X
X
X
X
Dout at K Dout at K Dout at K Dout at K
(t + 2.5) (t + 3.0) (t + 3.5) (t + 4.0)
X
L
Din at K Din at K Din at K Din at K
(t + 1) (t + 1.5) (t + 2) (t + 2.5)
X
X
X
X
Notes:
1. Internal burst counter is always fixed as four-bit.
2. X = “don’t care”; H = logic “1”; L = logic “0”.
3. A read operation is started when control signal R is active low
4. A write operation is started when control signal W is active low. Before entering into stop clock, all pending read and write com-
mands must be completed.
5. Consecutive read or write operations can be started only at every other K clock rising edge. If two read or write operations are
issued in consecutive K clock rising edges, the second one will be ignored.
6. If both R and W are active low after a NOP operation, the write operation will be ignored.
7. For timing definitions, refer to the AC Characteristics on page 17. Signals must have AC specifications at timings indicated in
parenthesis with respect to switching clocks K and K.
Integrated Silicon Solution, Inc.
9
Rev. 
05/14/09