IS61QDPB42M36 Datasheet, PDF (18/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs

72 Mb (2M x 36 & 4M x 18)
QUADP (Burst of 4) Synchronous SRAMs
Read and Deselect Cycles Timing Diagram
Read
Read
t_KHKH
t_KHKL t_KLKH
K
t_KHKH
K
SA
A1
t_AVKH
A2
t_KHAX
t_IVKH t_KHIX
R
NOP
NOP
Q (Data-Out)
Q1-1 Q1-2 Q1-3 Q1-4 Q2-1 Q2-2 Q2-3 Q2-4
t_CHQV
t_CHQX
t_CHQZ
t_CQHQV
t_CHCQX
t_CQHQX
CQ
t_CHCQV
t_CHCQX
CQ
t_CHCQV
Don’t Care
Undefined
Note: 1. Q1-1 refers to the output from address A1+0, Q1-2, Q1-3, Q1-4 refers to the output from address A1+1, A1+2, A1+3,
which is the nex internal burst addresses following A1+0.
2. Outputs are disabled one cycle after a NOP.
18
Integrated Silicon Solution, Inc.
Rev. A
05/14/09