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IS61QDPB42M36 Datasheet, PDF (1/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs | |||
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72 Mb (2M x 36 & 4M x 18)
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I 7 QUADP (Burst of 4) Synchronous SRAMs
Q
May 2009
Features
⢠2M x 36 or 4M x 18.
⢠On-chip delay-locked loop (DLL) for wide data
valid window.
⢠Separate read and write ports with concurrent
read and write operations.
⢠Synchronous pipeline read with late write opera-
tion.
⢠Double data rate (DDR) interface for read and
write input ports.
⢠Fixed 4-bit burst for read and write operations.
⢠Clock stop support.
⢠Two input clocks (K and K) for address and con-
trol registering at rising edges only.
⢠Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
⢠+1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
⢠HSTL input and output levels.
⢠Registered addresses, write and read controls,
byte writes, data in, and data outputs.
⢠Full data coherency.
⢠Boundary scan using limited set of JTAG 1149.1
functions.
⢠Byte write capability.
⢠Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
⢠Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 72Mb IS61QDPB42M36 and
IS61QDPB44M18 are synchronous, high-perfor-
mance CMOS static random access memory
(SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page 8 for a description of the basic opera-
tions of these QUADP (Burst of 4) SRAMs.
Read and write addresses are registered on alter-
nating rising edges of the K clock. Reads and writes
are performed in double data rate. The following are
registered internally on the rising edge of the K
clock:
⢠Read/write address
⢠Read enable
⢠Write enable
⢠Byte writes for burst addresses 1 and 3
⢠Data-in for burst addresses 1 and 3
The following are registered on the rising edge of
the K clock:
⢠Byte writes for burst addresses 2 and 4
⢠Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle after the write address. The first
data-in burst is clocked one cycle later than the write
command signal, and the second burst is timed to
the following rising edge of the K clock. Two full
clock cycles are required to complete a write opera-
tion.
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc.
1
Rev. A
05/14/09
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