IS61QDPB42M36 Datasheet, PDF (17/28 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUADP (Burst of 4) Synchronous SRAMs

72 Mb (2M x 36 & 4M x 18)
QUADP (Burst of 4) Synchronous SRAMs
AC CHARACTERISTICS (VDD = 1.8V 0.1V, TA=0 C to +70 C)
PARAMETER
Clock
Clock Cycle Time (K, K)
Clock Phase Jitter (K, K)
Clock High Time (K, K)
Clock Low Time (K, K)
Clock to Clock (K, K)
DLL Lock Time (K, K)
Doff Low period to DLL reset
Output Times
K, K High to Output Valid
K, K High to Output Hold
25 (400 MHz)
Min Max
tKHKH 2.50 7.5
tKC var
0.20
tKHKL 0.40
tKLKH 0.40
tKHKH 1.06
tKC lock 2048
tDoffLowToReset ₅
tCHQV
0.45
tCHQX -0.45
27 (375 MHz)
Min Max
2.66 7.5
0.20
0.40
0.40
1.13
2048
5
0.45
-0.45
30 (333 MHz)
Min Max
3.00 7.5
0.20
0.40
0.40
1.28
2048
5
0.45
-0.45
33 (300 MHz)
Min Max
3.30 7.5
0.20
0.40
0.40
1.40
2048
5
0.45
-0.45
unit notes
ns
ns
4
cycles
ns
ns
cycles 5
ns
ns
ns
K, K High to Echo Clock Valid tCHCQV
0.45
0.45
0.45
0.45 ns
K, K High to Echo Clock Hold tCHCQX -0.45
-0.45
-0.45
-0.45
ns
CQ, CQ High to Output Valid tCQHQV
0.20
0.20
0.20
0.20 ns
6
CQ, CQ High to Output Hold tCQHQX -0.20
-0.20
-0.20
-0.20
ns
6
K, High to Output High-Z
tCHQZ
0.45
0.45
0.45
0.45 ns
K, High to Output Low-Z
tCHQX1 -0.45
-0.45
-0.45
-0.45
ns
Setup Times
Address valid to K rising edge tAVKH 0.40
0.40
0.40
0.40
Control inputs valid to K rising
edge
tIVKH 0.40
0.40
0.40
0.40
Data-in valid to K, K rising
edge
tDVKH 0.28
0.28
0.28
0.28
Hold Times
ns
ns
2
ns
ns
K rising edge to address hold tKHAX 0.40
0.40
0.40
0.40
ns
K rising edge to control inputs
hold
tKHIX 0.40
0.40
0.40
0.40
ns
K, K rising edge to data-in
hold
tKHDX 0.28
0.28
0.28
0.28
ns
Notes:
1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW0,BW1 and (BW2, BW3, also for x36)
3. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test
conditions (0 C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70 C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. Vdd slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once Vdd and
input clock are stable.
6. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ns variation from
echo clock to data. The data sheet parameters reflect tester guard bands and test setup variations
Integrated Silicon Solution, Inc.
17
Rev. A
05/14/09