IS62LV1288LL Datasheet, PDF (8/10 Pages) Integrated Silicon Solution, Inc – 128K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM

IS62LV1288LL
ISSI ^®
WRITE CYCLE NO. 2 (WE, Controlled: OE is HIGH during Write Cycle)^(1,2)
tWC
ADDRESS
OE
CE1
CE2
WE
DOUT
DIN
tSCE1
tHA
tSCE2
tAW
tPWE1, 2
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW during Write Cycle)^(1,2)
tWC
ADDRESS
OE
CE1
CE2
WE
DOUT
DIN
tSCE1
tHA
tSCE2
tAW
tPWE1, 2
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/22/01