IS61SPD25632T Datasheet, PDF (8/22 Pages) Integrated Silicon Solution, Inc – 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM

IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
NC
NC
NC
VCCQ
GND
NC
NC
DQb1
DQb2
GND
VCCQ
DQb3
DQb4
VCC
VCC
NC
GND
DQb5
DQb6
VCCQ
GND
DQb7
DQb8
DQPb
NC
GND
VCCQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A17
NC
NC
VCCQ
GND
NC
DQPa
DQa8
DQa7
GND
VCCQ
DQa6
DQa5
GND
NC
VCC
ZZ
DQa4
DQa3
VCCQ
GND
DQa2
DQa1
NC
NC
GND
VCCQ
NC
NC
NC
ISSI ^®
512K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A18
Synchronous Address Inputs
CLK
ADSP
ADSC
ADV
BWa-BWb
BWE
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
8
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQb
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply:
+3.3V or 2.5V
ZZ
Snooze Enable
DQPa-DQPb Parity Data I/O DQPa is parity for DQa1-8;
DQPb is parity for DQb1-8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01