IS61SPD25632T Datasheet, PDF (10/22 Pages) Integrated Silicon Solution, Inc – 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM

IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ISSI ^®
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Symbol Parameter
TBIAS
Temperature Under Bias
TSTG
Storage Temperature
PD
Power Dissipation
IOUT
Output Current (per I/O)
VIN, VOUT Voltage Relative to GND for I/O Pins
VIN
Voltage Relative to GND for
for Address and Control Inputs
Value
–40 to +85
–55 to +150
1.6
100
–0.5 to VCCQ + 0.5
–0.5 to VCC + 0.5
Unit
°C
°C
W
mA
V
V
VCC
Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01