IS61SPD25632T Datasheet, PDF (15/22 Pages) Integrated Silicon Solution, Inc – 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM

IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-166*
Min. Max.
tKC
Cycle Time
6
—
tKH
Clock High Pulse Width
2.3
—
tKL
Clock Low Pulse Width
2.3
—
tAS
Address Setup Time
1.5
—
tSS
Address Status Setup Time
1.5
—
tWS Write Setup Time
1.5
—
tDS
Data In Setup Time
1.5
—
tCES Chip Enable Setup Time
1.5
—
tAVS Address Advance Setup Time 1.5
—
tAH
Address Hold Time
0.5
—
tSH
Address Status Hold Time
0.5
—
tDH
Data In Hold Time
0.5
—
tWH Write Hold Time
0.5
—
tCEH Chip Enable Hold Time
0.5
—
tAVH Address Advance Hold Time
0.5
—
*This speed available only in SPD version
-150
Min. Max.
6.7
—
2.5
—
2.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
-133
Min. Max.
7.5
—
2.8
—
2.8
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ISSI ^®
-100
Min. Max.
Unit
10
—
ns
3
—
ns
3
—
ns
2
—
ns
2
—
ns
2
—
ns
2
—
ns
2
—
ns
2
—
ns
0.5
—
ns
0.5
—
ns
0.5
—
ns
0.5
—
ns
0.5
—
ns
0.5
—
ns
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
PRELIMINARY INFORMATION Rev. 00A
04/17/01