IS61SPD25632T Datasheet, PDF (12/22 Pages) Integrated Silicon Solution, Inc – 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM

IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
CAPACITANCE^(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
6
8
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Unit
pF
pF
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V for 3.3V I/O
VCCQ/2V for 2.5V I/O
See Figures 1 and 2
ISSI ^®
AC TEST LOADS
ZO = 50Ω
Output
Buffer
50Ω
1.5V for 3,3V I/O
VCCQ/2V for 2.5V I/O
Figure 1
3.3V for 3.3V I/O
/2.5V for 2.5v I/O
OUTPUT
317 Ω/1667 Ω
5 pF
Including
jig and
scope
351 Ω/1538 Ω
Figure 2
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01