IS61NLF204836B Datasheet, PDF (7/38 Pages) Integrated Silicon Solution, Inc – 100 percent bus utilization

IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B 
119-PIN PBGA PACKAGE CONFIGURATION 4M x 18 (TOP VIEW)
1
2
3
4
A
VDDQ
A
A
A
B
NC
CE2
A
ADV
C
NC
A
A
VDD
D
DQb
NC
VSS
NC
E
NC
DQb
VSS
CE
F
VDDQ
NC
VSS
OE
G
NC
DQb
BWb
A
H
DQb
NC
VSS
WE
J
VDDQ
VDD
NC
VDD
K
NC
DQb
VSS
CLK
L
DQb
NC
M
VDDQ
DQb
NC
VSS
NC
CKE
N
DQb
NC
VSS
A1*
P
NC
DQPb
VSS
A0*
R
NC
A
MODE
VDD
T
A
A
A
A
U
VDDQ
TMS
TDI
TCK
5
A
A
A
VSS
VSS
VSS
NC
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
TDO
6
A
CE2
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
7
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A
Synchronous Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWa-BWb
Synchronous Byte Write Inputs
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQa-DQb
DQPa-DQPb
VDDQ
Vss
Burst Sequence Selection
JTAG Pins
Power Supply
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data
Inputs/Outputs
I/O Power Supply
Ground
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. 00C
02/20/2013