IS61NLF204836B Datasheet, PDF (27/38 Pages) Integrated Silicon Solution, Inc – 100 percent bus utilization

IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B 
INSTRUCTION CODES
Code
Instruction
000
EXTEST
001
IDCODE
010
SAMPLE-Z
011
RESERVED
100
SAMPLE/PRELOAD
101
RESERVED
110
RESERVED
111
BYPASS
Description
Captures the Input/Output ring contents. Places the boundary scan register be-
tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
Run Test/Idle ¹
0
Select DR ¹
0
1 _{Capture DR}
0
Shift DR
10
Exit1 DR ¹
0
Pause DR
10
0 ^{Exit2 DR}
1
1 _{Update DR}
0
Select IR ¹
0
1 _{Capture IR}
0
Shift IR
10
Exit1 IR ¹
0
Pause IR
10
0 ^{Exit2 IR}
1
1 _{Update IR}
0
Integrated Silicon Solution, Inc. — www.issi.com
27
Rev. 00C
02/20/2013