IS61NLF204836B Datasheet, PDF (25/38 Pages) Integrated Silicon Solution, Inc – 100 percent bus utilization

IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B 
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the cur-
rent state of the TAP state machine (see TAP Controller
State Diagram). The output changes on the falling edge
of TCK and TDO is connected to the Least Significant Bit
(LSB) of any register.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (Vdd) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on
the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the in-
struction register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram)  At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern
to allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass reg-
ister is set LOW (Vss) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed be-
tween the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Scan Register Sizes
Register
Bit Size
Name
(x18)
Instruction
3
Bypass
1
ID
32
Boundary Scan
75
Bit Size
(x36)
3
1
32
75
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE com-
mand is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field
Description
Revision Number  (31:28) Reserved for version number.
Device Depth  (27:23)
Defines depth of SRAM. 2M or 4M
Device Width  (22:18)
Defines Width of the SRAM. x36 or x18
ISSI Device ID  (17:12)
Reserved for future use.
ISSI JEDEC ID  (11:1)
Allows unique identification of SRAM vendor.
ID Register Presence  (0) Indicate the presence of an ID register.
2M x 36
xxxx
01010
00100
xxxxx
00001010101
1
4M x 18
xxxx
01011
00011
xxxxx
00001010101
1
Integrated Silicon Solution, Inc. — www.issi.com
25
Rev. 00C
02/20/2013