IS61LV256AL_09 Datasheet, PDF (7/12 Pages) Integrated Silicon Solution, Inc – 32K x 8 LOW VOLTAGE CMOS STATIC RAM

IS61LV256AL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol
twc
tsce
taw

tha

tsa
tpwe1
tpwe2
tsd
thd
thzwe⁽³⁾
tlzwe⁽³⁾
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold
from Write End
Address Setup Time
WE Pulse Width (OE HIGH)
WE Pulse Width (OE LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-10 ns
Min. Max.
10 —
8—
8—
0—
0—
7—
10 —
6.5 —
0—
— 3.5
0—
-12 ns
Min. Max. Unit
12 —
ns
8—
ns
8—
ns
0—
ns
0—
ns
8—
ns
12 —
ns
7—
ns
0—
ns
—5
ns
0—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW.All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or
falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) ^(1 )
t WC
ADDRESS
CE
WE
DOUT
DIN
VALID ADDRESS
t SA
t SCE
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
CE_WR1.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev.  C
07/29/09