IS61LV256AL_09 Datasheet, PDF (2/12 Pages) Integrated Silicon Solution, Inc – 32K x 8 LOW VOLTAGE CMOS STATIC RAM

IS61LV256AL
PIN CONFIGURATION
28-Pin SOJ
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
28 VDD
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
PIN CONFIGURATION
28-Pin TSOP (Type I)
OE 22
A11 23
A9 24
A8 25
A13 26
WE 27
VDD 28
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 GND
13 I/O2
12 I/O1
11 I/O0
10 A0
9 A1
8 A2
PIN DESCRIPTIONS
A0-A14 Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7 Input/Output
Vdd
Power
GND Ground
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE CE OE I/O Operation Vdd Current
XHX
High-Z
Isb1, Isb2
HLH
High-Z
Icc
HL L
Dout
Icc
LLX
Din
Icc
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Symbol Parameter
Value Unit
Vdd
Power Supply Voltage Relative to GND
–0.5 to +4.6 V
Vterm Terminal Voltage with Respect to GND
–0.5 to +4.6 V
Tstg
Storage Temperature
–65 to +150 °C
Pd
Power Dissipation
1
W
Iout
DC Output Current
±20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent dam-
age to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.  C
07/29/09