IS61LV256AL_09 Datasheet, PDF (5/12 Pages) Integrated Silicon Solution, Inc – 32K x 8 LOW VOLTAGE CMOS STATIC RAM

IS61LV256AL
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
-10 ns
Symbol
Parameter
Min. Max.
trc
Read Cycle Time
10 —
taa
Address Access Time
— 10
toha
Output Hold Time
2—
tace
CE Access Time
— 10
tdoe
OE Access Time
—5
tlzoe⁽²⁾
OE to Low-Z Output
0—
thzoe⁽²⁾
OE to High-Z Output
—5
tlzce⁽²⁾
CE to Low-Z Output
3—
thzce⁽²⁾
CE to High-Z Output
—5
tpu⁽³⁾
CE to Power-Up
0—
tpd⁽³⁾
CE to Power-Down
— 10
-12 ns
Min. Max. Unit
12 —
ns
— 12
ns
2—
ns
— 12
ns
—5
ns
0—
ns
—5
ns
3—
ns
—6
ns
0—
ns
— 12
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2.Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
3.3V
319 Ω
3.3V
319 Ω
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1.     Figure 2.
353 Ω
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev.  C
07/29/09