IS61QDB22M36 Datasheet, PDF (4/27 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs

372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI ^®
Block Diagram
D (Data-In)
36 (or 18)
Data
Reg
Address
20 (or 21)
Add
Reg
20 (or 21)
R
W
BW_x
4 (or 2)
Control
Logic
36 (or 18) 36 (or 18)
Write Driver
2M x 36
(4M x 18)
Memory
Array
72
(or 36)
K
K
Clock
C
Gen
C
Select Output Control
72
(or 36)
36 (or 18)
Q (Data-Out)
CQ, CQ
(Echo Clock Out)
SRAM Features
Read Operations
The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R in active
low state at the rising edge of the K clock. A second set of clocks, C and C, are used to control the timing to
the outputs. A set of free-running echo clocks, CQ and CQ, are produced internally with timings identical to
the data-outs. The echo clocks can be used as data capture clocks by the receiver device.
When the C and C clocks are connected high, the K and K clocks assume the function of those clocks. In this
case, the data corresponding to the first address is clocked 1.5 cycles later by the rising edge of the K clock.
The data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the K
clock.
A NOP operation (R is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every rising edge of the K clock whenever W is low. The write
address is provided 0.5 cycles later, registered by the rising edge of K. Again, the write always occurs in
bursts of two.
The write data is provided in an ‘early write’ mode; that is, the data-in corresponding to the first address of the
burst, is presented 0.5 cycles earlier or at the rising edge of the preceding K clock. The data-in corresponding
to the second write burst address follows next, registered by the rising edge of K.
The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into
the array on the following write cycle. A read cycle to the last write address produces data from the write
buffers. Similarly, a read address followed by the same write address produces the latest write data. The
SRAM maintains data coherency.
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09