IS61QDB22M36 Datasheet, PDF (18/27 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs

372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI ^®
Write and NOP Timing Diagram
Write
Write NOP
t_KLKH
t_KHKH
t_KHKL
K
t_KHKH
K
SA
t_IVKH
W
t_IVKH
A1
t_KHIX
t_KHIX
t_AVKH
A2
t_KHIX
BW
D(Data In)
D1-1 D1-2 D2-1 D2-2
Write NOP
t_KHAX
A3
t_DVKH
t_KHDX
D3-1 D3-2
Don’t Care
Undefined
Notes: 1. D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1 (that is, the next internal
burst address following A1+0).
2. BWx assumed active.
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09