IS61QDB22M36 Datasheet, PDF (16/27 Pages) Integrated Silicon Solution, Inc – 72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs

72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
AC Characteristics (T_A = 0 to + 70C, V_DD = 1.8V -5%, +5%)
Parameter
Symbol
Clock
Cycle time (K, K, C, C)
t_KHKH
Clock phase jitter (K, K, C, C)
t_KC-VAR
Clock high pulse (K, K, C, C)
t_KHKL
Clock low pulse (K, K, C, C)
t_KLKH
Clock to clock (K_H>K_H, C_H>C_H)
t_KHKH
Clock to data clock (K_H>C_H, K_H>C_H) t_KHCH
DLL lock (K, C)
t_KC-lock
Doff Low period to DLL reset
Output Times
C, C high to output valid
C, C high to output hold
C, C high to echo clock valid
C, C high to echo clock hold
CQ, CQ High to output valid
CQ, CQ high to output hold
C High to output high-Z
C High to output low-Z
Setup Times
t_CHQV
t_CHQX
t_CHCQV
t_CHCQX
t_CQHQV
t_CQHQX
t_CHQZ
t_CHQX1
Address valid to K, K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
t_AVKH
t_IVKH
t_DVKH
K rising edge to address hold
K rising edge to Control Inputs Hold
K, K rising edge to data-in hold
t_KHAX
t_KHIX
t_KHDX
40
(250MHz)
Min Max
4.0 7.5
0.2
1.6
1.6
1.8
0.0 0.8
1024
5
0.45
-0.45
0.40
-0.40
0.30
-0.30
0.45
-0.45
0.35 —
0.35 —
0.35 —
0.35 —
0.35 —
0.35 —
50
(200MHz)
Min Max
5.0 7.5
0.2
2.0
2.0
2.2
0.0 0.8
1024
5
0.45
-0.45
0.4
-0.40
0.35
-0.35
0.45
-0.45
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
Units Notes
ns
ns
ns
ns
ns
ns
cycle
ns
ns 1, 3
ns 1, 3
ns 3
ns
3
ns 1, 3
ns 1, 3
ns 1, 3
ns 1, 3
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
1. See AC Test Loading on page 15.
2. During normal operation, V_IH, V_IL, T_RISE, and T_FALL of inputs must be within 20% of V_IH, V_IL, T_RISE, and T_FALL of clock.
3. If C, C are tied high, then K, K become the references for C, C timing parameters.4. Specs cover -40C to +85C temperature range.
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09