IS66WVE2M16EALL Datasheet, PDF (22/31 Pages) Integrated Silicon Solution, Inc – Asynchronous and page mode interface

IS66/67WVE2M16EALL/BLL/CLL
Table 13 . Asynchronous WRITE Cycle Timing Requirements
Symbol
Parameter
-55
Min
Max
-70
Min
Max
Unit
Notes
t_AS
Address setup Time
0
0
ns
t_AW
Address valid to end of write
55
70
ns
t_BW
Byte select to end of write
55
70
ns
t_CEM
Maximum CE# pulse width
8
8
us
t_CPH
CE# HIGH time during write
5
5
ns
t_CW
Chip enable to end of Write
55
70
ns
t_DH
Data hold from write time
0
0
ns
t_DW
Data write setup time
23
23
ns
t_LZ
Chip enable to Low-Z output
10
10
ns
1
t_OW
End write to Low-Z output
5
5
ns
1
t_WC
Write cycle time
55
70
ns
t_WHZ
Write to High-Z output
8
8
ns
2
t_WP
Write pulse width
46
46
ns
t_WPH
Write pulse width HIGH
10
10
ns
t_WR
Write recovery time
0
0
ns
3
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The
Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
3. Write address is valid prior to or coincident with CE# LOW transition and is valid prior to or coincident with
CE# HIGH transition.
Rev. 0D | November 2014
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